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NS9750 Hardware Reference
Dynamic Memory Write Recovery Time register
Address: A070 0044
The Dynamic Memory Write Recovery Time register allows you to program the write
recovery time, t
WR
. It is recommended that this register be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode. This value
normally is found in SDRAM datasheets as t
WR
, t
DPL
, t
RWL
, or t
RDL
.
Note:
The Dynamic Memory Write Recovery Time register is used for all four
dynamic memory chip selects. The worst case value for all chip selects
must be programmed.
Register bit assignment
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W WR Write recovery time (t
WR
, t
DPL
, t
RWL
, or t
RDL
)
0x0–0xE
n+1 clock cycles, where the delay is in CLK cycles.
0xF
16 clock cycles (reset value on reset_n)
Table 149: Dynamic Memory Write Recovery TIme register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WR