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Memory Controller
Table 134 shows the outputs for the memory controller and the corresponding inputs
to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects).
66 16 7
55 15 6
44 14 5
33 13 4
22 12 3
11 11 2
0 0 10 **
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 25 25
13 BA0 24 24
12 12 23 -
11 11 22 -
10 10/AP 21 AP
9 9 20 10
88 19 9
77 18 8
66 17 7
55 16 6
44 15 5
33 14 4
22 13 3
Table 134: Address mapping for 256M SDRAM (32Mx8, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 133: Address mapping for 256M SDRAM (16Mx16, BRC)