Filter
Top Products
System control processor (CP15) registers
54
NS9750 Hardware Reference
All CP15 register bits that are defined and contain state are set to 0 by reset, with
these exceptions:
The V bit is set to 0 at reset if the VINITHI signal is low, and set to 1 if the
VINITHI signal is high.
The B bit is set to 0 at reset if the BIGENDINIT signal is low, and set to 1 if the
BIGENDINIT signal is high.
4 Reserved Reserved
5 Data fault status (based on opcode_2 value) Data fault status (based on opcode_2 value)
6 Instruction fault status (based on opcode_2
value)
Instruction fault status (based on opcode_2
value)
7 Cache operations Cache operations
8 Unpredictable TLB
9 Cache lockdown (based on
CRm value) Cache lockdown
10 TLB lockdown TLB lockdown
11 and 12 Reserved Reserved
13 FCSE PID (based on
opcode_2 value)
FCSE = Fast context switch extension
PID = Process identifier
FCSE PID (based on
opcode_2 value)
FCSE = Fast context switch extension
PID = Process identifier
13 Context ID (based on
opcode_2 value) Context ID (based on opcode_2 value)
14 Reserved Reserved
15 Test configuration Test configuration
Register Reads Writes
Table 18: CP15 register summary