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About NS9750
input reset pin can be driven by a system reset circuit or a simple power-on reset
circuit.
RESET_DONE as an input
Used at bootup only:
When set to 0, the system boots from SDRAM through the serial SPI EEPROM.
When set to 1, the system boots from Flash/ROM. This is the default.
RESET_DONE as an output
Sets to 1, per Step 6 in the boot sequence.
If the system is booting from serial EEPROM through the SPI port, the boot program
must be loaded into the SDRAM before the CPU is released from reset. The memory
controller is powered up with dy_cs_n[0] enabled with a default set of SDRAM
configurations. The default address range for
dy_cs_n[0] is from 0x0000 0000. The other
chip selects are disabled.
Boot sequence
1 When the system reset turns to inactive, the reset signal to the CPU is still held
active.
2 An I/O module on the peripheral bus (BBus) reads from a serial ROM device that
contains the memory controller settings and the boot program.
3 The BBus-to-AHB bridge requests and gets the system bus.
4 The memory controller settings are read from the serial EEPROM and used to
initialize the memory controller.
5 The BBus-to-AHB bridge loads the boot program into the SDRAM, starting at
address 0.
6 The reset signal going to the CPU is released once the boot program is loaded.
RESET_DONE is now set to 1.
7 The CPU begins to execute code from address 0x0000 0000.