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System control processor (CP15) registers
66
NS9750 Hardware Reference
Wait for interrupt Drains the contents of the write buffers, puts the processor
into low-power state, and stops the processor from
executing further instructions until an interrupt (or debug
request) occurs. When an interrupt does occur, the
MCR
instruction completes, and the IRQ or FIRQ handler is
entered as normal.
The return link in
R14_irq or R14_fiq contains the address of
the
MCR instruction plus eight, so the typical instruction
used for interrupt return (SUBS PC,R14,#4) returns to the
instruction following the
MCR.
Function/operation Data format Instruction
Invalidate ICache and DCache SBZ
MCR p15, 0, Rd, c7, c7, 0
Invalidate ICache SBZ
MCR p15, 0, Rd, c7, c5, 0
Invalidate ICache single entry (MVA) MVA
MCR p15, 0, Rd, c7, c5, 1
Invalidate ICache single entry (set/way) Set/Way
MCR p15, 0, Rd, c7, c5, 2
Prefetch ICache line (MVA) MVA
MCR p15, 0, Rd, c7, c13, 1
Invalidate DCache SBZ
MCR p15, 0, Rd, c7, c6, 0
Invalidate DCache single entry (MVA) MVA
MCR p15, 0, Rd, c7, c6, 1
Invalidate DCache single entry (set/way) Set/Way
MCR p15, 0, Rd, c7, c6, 2
Clean DCache single entry (MVA) MVA
MCR p15, 0, Rd, c7, c10, 1
Clean DCache single entry (set/way) Set/Way
MCR p15, 0, Rd, c7, C10, 2
Test and clean DCache n/a
MRC p15, 0, Rd, c7, c10, 3
Clean and invalidate DCache entry (MVA) MVA
MCR p15, 0, Rd, c7, c14, 1
Clean and invalidate DCache entry (set/way) Set/Way
MCR p15, 0, Rd, c7, c14, 2
Test, clean, and invalidate DCache n/a
MRC p15, 0, Rd, c7, c14, 3
Drain write buffer SBZ
MCR p15, 0, Rd, c7, c10, 4
Wait for interrupt SBZ
MCR p15, 0, Rd, c7, c0, 4
Table 27: R7: Cache operations
Function Description
Table 26: Cache Operations register function descriptions