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PCI-to-AHB Bridge
PCI Arbiter Interrupt Enable register
Address: A030 0008
The PCI Arbiter Interrupt Enable register has an enable bit for each of the interrupt
status bits in the PCI Arbiter Interrupt Status register. Set these bits to 1 to allow the
associated interrupt status bit to cause an interrupt to the system.
Register bit assignment
D05 R/C CCLKRUN 0 Restart CardBus clock
Used for CardBus Applications only. Indicates that an
external CardBus card has asserted CardBus
CCLKRUN# to request that the CardBus clock be
restarted.
D04 R/C PCISERR 0 An
SERR signal has been received from an external PCI
agent.
D03 R/C PCIBRK_M3 0 External master 3 broken
D02 R/C PCIBRK_M2 0 External master 2 broken
D01 R/C PCIBRK_M1 0 External master 1 broken
D00 R/C PCIBRK_M0 0 PCI-to-AHB bridge broken
BIts Access Mnemonic Reset Description
D31:06
Read only;
hard-wired to
0
Reserved N/A N/A
Table 262: PCI Arbiter Interrupt Enable register
Bits Access Mnemonic Reset Description
Table 261: PCI Arbiter Interrupt Status register
Reserved
EN_
CCLK
RUN
EN_
PCI
SERR
EN_P
BRK_
M3
EN_P
BRK_
M0
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
EN_P
BRK_
M2
EN_P
BRK_
M1