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565
LCD Controller
Depending on the LCD type and mode, the unpacked data can represent one of the
following:
An actual true display gray or color value
An address to a 256 x 16 bit wide palette RAM gray or color value
With STN displays, either a value obtained from the addressed palette location or the
true value is passed to the grayscaling generators. The hardware-coded grayscale
algorithm logic sequences the addressed pixels activity over a programmed number
of frames to provide the proper display appearance.
With TFT displays, either an addressed palette value or true color value is passed
directly to the output display drivers, bypassing the grayscaling algorithm logic.
Clocks
The NS9750 LCD controller requires separate AHB (HCLK) and LCD (CLCDCLK) input
clocks. The source of
CLCDCLK is programmable using the LCD panel select field in the
Clock Configuration register. Table 343 shows the clock selections.
The LCD controller uses
CLCDCLK internally. The clock sent to the LCD panel (CLCP)
normally is derived from
CLCDCLK using the PCD (panel clock divisor) value in the
LCDTiming2 register (see page 586). The LCD controller also can bypass the internal
clock divider controlled by PCD and use
CLCDCLK as CLCP directly by setting the BCD
(bypass pixel clock divider) bit to 1 in the LCDTiming2 register (see page 584).
LCD panel clock select CLCDCLK
000 HCLK
001 HCLK/2
010 HCLK/4
011 HCLK/8
1xx lcdclk/2
Note: lcdclk is an external clock input to NS9750. A
divided-by-2 version of this value is sent to the
LCD controller.
Table 343: CLCDCLK selection