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Dynamic memory controller
168
NS9750 Hardware Reference
Table 95 shows the outputs from the memory controller and the corresponding inputs
to the 64 M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Table 96 shows the outputs from the memory controller and the corresponding inputs
to the 128M SDRAM (4Mx32, pins 13 and 14 used as bank selects).
Output address
(ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 12 12
12---
11 11 24 -
10 10/AP 23 AP
99 22 -
8 8 21 10
77 20 9
66 19 8
55 18 7
44 17 6
33 16 5
22 15 4
11 14 3
00 13 2
Table 95: Address mapping for 64M SDRAM (8Mx8, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 10 10
12---
Table 96: Address mapping for 128M SDRAM (4Mx32, RBC)