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DEFINITY Enterprise Communications Server Release 5
Maintenance and Test for R5vs/si
555-230-123
Issue 1
April 1997
Maintenance Object Repair Procedures
Page 10-1188PROCR (Processor Circuit Pack)
10
This test causes service to be disrupted for about seven seconds on the TN773
and for about one second on the TN786B. During this time, the system does not
respond to any user action.
This test checks to see if the 80286/386 processor watch-dog sanity timer is
functioning correctly. The processor intentionally allows the sanity timer to time
out. If the processor detects itself being reset, the test passes, and the processor
continues to execute normally. If the processor does not detect a reset, the test
has failed. If this test continues to fail, the processor pack should be replaced as
soon as possible. The sanity timer is not critical to system operation, but it is
needed for processor recovery if the processor stops functioning.
Table 10-365. TEST #83 Processor Sanity Timer Test
Error
Code
Test
Result Description/ Recommendation
1000 ABORT System software resources required for this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5 times.
1029
2014
2015
2016
2017
2018
2020
2022
2024
2025
2051
ABORT Refer to STBY-SPE Maintenance documentation for a description of these
error codes.
FAIL The sanity timer did not time out as expected. The system continues to
function normally. If the processor gets into an infinite loop, the reset
CANNOT be detected, and the system DOES NOT reboot itself to clear the
problem.
1. Retry the command at 1-minute intervals a maximum of 5 times.
2. If test continues to fail, the Processor circuit pack should be replaced
as soon as possible.
PASS The sanity timer went off as expected. The system continues to function
normally. If the processor gets into an infinite loop, the reset IS detected,
and the system reboots itself to clear the problem.
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