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DEFINITY Enterprise Communications Server Release 5
Maintenance and Test for R5vs/si
555-230-123
Issue 1
April 1997
Maintenance Object Repair Procedures
Page 10-1194PROCR (TN790 RISC Processor Circuit Pack)
10
This test verifies that the Processor Instruction and Data Caches are functional.
Some errors in the caches will simply reduce performance by forcing instructions
or data to be read from memory more often than would normally be necessary. In
any case, cache problems are serious and the Processor circuit pack must be
replaced as soon as possible if they are detected.
Processor Cache Audit (#896)
This nondestructive audit checks the state of the Cache Parity bit maintained by
the RISC CPU. If this bit is set, there may be problems with either the CPU, the
Instruction, or Data Cache. An indication of bad cache parity won’t itself mean
that the system won’t operate, but minor to severe performance degradation may
be present. For example, a single bad bit in either cache could cause this bit to
be set. If the faulty word is seldom accessed, the impact will be small. If the bit is
accessed frequently, there could be serious problems with much, or all, of the
cache (stuck data bit) with the only direct indication again being the cache parity
error or cache test error.
Table 10-369. Test #895 Processor Cache Test
Error
Code
Test
Result Description/ Recommendation
100 ABORT The test did not complete within the allowable time period.
1. Retry the command.
1029
2014
2015
2016
2017
2018
2020
2022
2024
2025
2051
ABORT Refer to STBY-SPE Maintenance documentation for a description of these
error codes.
2500 ABORT Internal system error
1. Retry the command.
FAIL The Processor cache is not functioning correctly.
1. Replace the Processor circuit pack immediately.
PASS The cache portion of the Processor circuit pack is operating correctly.
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