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DEFINITY Enterprise Communications Server Release 5
Maintenance and Test for R5vs/si
555-230-123
Issue 1
April 1997
Maintenance Object Repair Procedures
Page 10-1334SYNC (Synchronization)
10
■ If the problem still persists, switch the Tone-Clock in the
slave port network back to the previous configuration. Then,
switch Expansion Interface Links via the set expansion-link
PCSS command.
■ If the problem still persists, switch the Expansion Interface
Links back to the previous configuration via the set
expansion-link PCSS. Then, switch the Tone-Clock circuit
packs in the master port network.
■ If the problem still persists, switch the Tone-Clock circuit
packs in the master port network back to the previous
configuration. If the system synchronization reference is a
Tone-Clock circuit pack, follow normal escalation
procedures. If the system synchronization reference is a DS1
interface circuit pack, administer a different DS1 interface
circuit pack as the primary synchronization reference.
4.Standard system:—Error 2049:
■ Test the Tone-Clock circuit packs in the master and slave
port networks via the test tone/clock PC long command.
Check the Error Log for TDM-CLK errors and verify that TDM
Bus Clock Test #148 passes successfully. If Test #148 fails
with an Error Code 2 through 32, refer to “TDM-CLK” to
resolve the problem. If not, continue with the following steps.
■ If the master and slave Tone-Clock circuit packs do not fail
TDM Bus Clock Test #150 (PPM Inquiry), replace the
Expansion Interface circuit packs in the system.
■ If the system synchronization reference is a Tone-Clock
circuit pack and the master Tone-Clock circuit pack fails
TDM Bus Clock Test #150, follow the steps listed in
“TDM-CLK” to replace the master Tone-Clock circuit pack.
■ If the system synchronization reference is a DS1 interface
circuit pack and the master Tone-Clock circuit pack fails
TDM Bus Clock Test #150, the primary or secondary (if
administered) synchronization references are not providing
valid timing signals for the system. Check the system
synchronization references administered, and follow the
steps outlined in note (a) if the primary synchronization
reference is providing timing for the system or note (c) if the
secondary synchronization reference is providing timing for
the system.
■ If the slave Tone-Clock circuit pack fails the TDM Bus Clock
Test #150 but the master Tone-Clock does not fail this test,
the master Tone-Clock circuit pack must be replaced. Follow
the Tone-Clock replacement steps listed in the “TDM-CLK”.
If SLIP errors remain follow SLIP ANALYSIS.